How to Eliminate or Suppress the Miller Effect

The Miller effect comes from the parasitic Miller capacitance Cgd between gate and drain of MOSFET. During switching, the drain‑voltage swing couples current into the gate loop. It causes gate voltage platform (Miller plateau), slows switching speed, increases switching loss, may induce false turn‑on, EMI noise and even device damage.

We cannot completely erase the physical Miller capacitance, so the goal in engineering is suppress, not fully eliminate.

1. Gate‑resistor optimization (most commonly used method)

1.1 Principle

Add appropriate gate resistor Rg in series to the gate driving loop. It changes gate charging / discharging speed, suppresses the current spike caused by Miller capacitance.

1.2 Usage

Increase Rg: suppress Miller plateau oscillation, reduce EMI, but switching loss will rise.
Reduce Rg: faster switching, lower switching loss, but aggravate Miller oscillation and risk of false turn‑on.

1.3 Practical tip

Do not use too large Rg. Split into two resistors: one resistor for turn‑on, another smaller resistor plus diode for turn‑off, to separate turn‑on / turn‑off driving strength. This balances loss and anti‑Miller performance.

2. Add Miller clamp (gate clamp)

2.1 Principle

Add a dedicated clamp transistor or simple diode‑clamp circuit between gate and source. When Miller current injects to gate, the clamp pulls gate voltage firmly down to source potential, preventing false turn‑on.

2.2 Typical scenario

Half‑bridge / LLC circuits, where the lower MOS may be falsely turned‑on by Miller effect from upper‑tube switching. Many dedicated gate‑driver ICs integrate internal Miller‑clamp pin.

2.3 Advantage: Very effective against parasitic false turn‑on; does not greatly sacrifice switching speed.

3. Use gate‑drive power supply with negative voltage

3.1 Principle

Drive MOSFET with negative gate‑source voltage (‑5V ~‑8V) when turning off. Even if Miller current injects charge to gate, the gate‑source voltage still stays well below MOS threshold voltage, avoiding accidental turn‑on.

3.2 Application

High‑power half‑bridge, full‑bridge, SiC MOS power converters.

3.3 Disadvantage: Need extra negative power rail, increases circuit complexity and BOM cost.

4. PCB layout optimization (critical hardware measure)

4.1 Minimize gate‑drain coupling loop

Shorten gate trace length; reduce overlapping area between gate trace and drain power copper, to lower physical parasitic Cgd coupling on PCB.

4.2 Reduce gate‑source loop impedance

Place gate‑resistor and gate‑driver IC close to MOSFET gate‑source pin. Keep gate‑source return path very short. Low‑impedance source path can quickly absorb Miller displacement current.

4.3 Power‑loop minimization

Make high‑current power loop as small as possible, suppress drain‑voltage sharp overshoot, reduce the amplitude of voltage change \(dV/dt\), which is the source of Miller current.

5. Device‑level selection

5.1 Select MOSFET with smaller intrinsic Cgd / Ciss ratio. Devices with low Miller charge Qgd have weaker Miller‑effect tendency.

5.2 For high‑frequency hard‑switching applications, prefer trench‑gate or shield‑gate SGT MOS; SiC MOS also has different Miller‑charge characteristics compared with silicon MOS.

Note: You cannot remove Cgd completely; you can only pick devices with better parameters.

6. Active Miller clamp built‑in driver IC

6.1 Many modern half‑bridge gate‑driver chips integrate active Miller clamp function inside. When MOS is in OFF state, internal low‑resistance switch pulls gate firmly to GND.

6.2 This removes requirement for negative power supply, widely used in LLC, PFC, motor‑drive circuits.

7. Common misconceptions

7.1 ❌ Cannot 100% eliminate Miller effect. It originates from internal parasitic capacitance of MOSFET, which is physical property of the chip. All methods are suppression techniques.

7.2 ❌ Simply increasing gate resistance infinitely is not good. Excessive Rg will sharply raise switching loss and temperature.

7.3 ❌ Only focus on peripheral circuit and ignore PCB layout. Bad layout will make all peripheral compensation circuits ineffective.

8. Quick selection guide for engineering

8.1 Low‑to‑medium power consumer power supply: Optimize Rg + good PCB layout.

8.2 Half‑bridge / LLC power supply: Use driver IC with integrated active Miller clamp.

8.3 High‑power industrial / SiC application: Active clamp + negative gate drive + optimized power loop.

Summary

Miller effect stems from MOS parasitic gate‑drain capacitance, cannot be completely eliminated.
Main suppression means: gate resistor adjustment, Miller clamp, negative turn‑off voltage, optimized PCB layout, selecting low‑Qgd MOSFET.
For half‑bridge topology, active Miller clamp is one of the most cost‑effective solutions.